1. Technical Field
The present disclosure relates to an image signal processing apparatus and method, and more particularly, to a image signal processing apparatus and method which minimizes the number of memory accesses and does not require a high memory bandwidth.
2. Discussion of the Related Art
An image signal captured by a video camera or a camcorder is transmitted to a display device such as a digital TV via an image signal processor. The image signal processor removes noise from the image signal, deinterlaces the image signal when the image signal is an interlaced image signal, and scales the image signal when necessary.
FIG. 1 is a block diagram of a conventional image signal processor. The image signal processor includes a memory 110, a bus 120, a plurality of interface units IF11, IF12, IF13 and IF14, an input unit 130, a noise removal unit 140, a deinterlacing unit 150, and a scaler 160. The image signal processor receives and processes an input image signal Si and outputs an output image signal So.
The image signal Si input to the image signal processor passes through the input unit 130, the interface units IF11 and the bus 120 and is then stored in the memory 110. The image signal Si stored in the memory is input to the noise removal unit 140 via the bus 120 and the interface unit IF12 to generate a filtered image signal. The filtered image signal is stored in the memory 110 via the interface unit IF12 and the bus 120. When the input image signal Si is an interlaced image signal, the filtered image signal is input to the deinterlacing unit 150 via the bus 120 and the interface unit IF13 to generate a deinterlaced image signal. The deinterlaced image signal passes through the interface unit IF13 and the bus 120 and is stored in the memory 110. The deinterlaced image signal stored in the memory 110 is input to the scaler 160 via the bus 120 and the interface unit IF14. The scaler 160 scales the image signal and outputs the scaled image signal as the output image signal So. The output image signal So is transmitted to a video processing block that performs, for example, graphic processing.
In the aforementioned image signal processing operation, frequent memory accesses are carried out. These memory accesses delay image signal processing. When processing a high definition (HD) image signal having a large data capacity, the experienced image signal processing delay is exacerbated.
The input image signal Si is stored in the form of multiple lines of video data in the memory 110. When the size of an image corresponding to the input image signal Si (i.e., the image size of the input image signal) is larger than the size of an image corresponding to the output image signal So (i.e., the image size of the output image signal), the scaler 160 should simultaneously read at least two lines of video data from the memory 110 for a single memory access. For example, when the image size of the input image signal Si is twice the image size of the output image signal, the scaler 160 should simultaneously read two lines of video data for each single memory access.
As the quantity of data read by the scaler 160 for a single memory access increases, a higher memory bandwidth is required. However, this becomes a problem in image signal processing because memory bandwidth is limited.
FIG. 2 is a block diagram of a conventional image signal processor used for a picture in picture (PIP) mode. To construct a double picture in the PIP mode, more than two kinds of image signals are required. A main picture of the double picture is formed from a main output image signal So1 generated by processing a main input image signal Si1 and a sub picture of the double picture is formed from a sub output image signal So2 generated by processing a sub input image signal Si2.
The image signal processor of FIG. 2 includes a memory 210, a bus 220, a plurality of interface units IF21 through IF28 and an output multiplexer 270. In FIG. 2, a first input unit 232, a first noise removal unit 242, a first deinterlacing unit 251 and a first scaler 262 process the main input image signal Si1 while the second input unit 234, a second noise removal unit 244, a second deinterlacing unit 254 and a second scaler 264 process the sub input image signal Si2.
The image signal processor of FIG. 2 should process a quantity of data larger than the quantity of data processed by the image signal processor of FIG. 1 in order to construct the PIP double picture. Accordingly, memory accesses should be performed more frequently and a higher memory bandwidth is required.
Thus, there is a need for an image signal processing apparatus and method which minimize the number of memory accesses and require a smaller memory bandwidth.